将二维材料制备成场效应晶体管是迄今为止可重复性最高、测试和制备方法最成熟的用于研究二维材料半导体性质的手段。自2004年石墨烯背栅薄膜晶体管结构被发明以来，机械剥离二维材料背栅晶体管结构已被应用于能带结构、电子自旋、光探测器、气体及各类有机分子探测器等各项研究中。 为得到最佳性能的二维材料机械剥离薄膜，文献中通常使用Si/SiO₂衬底作为二维材料的背栅晶体管衬底。衬底中SiO₂厚度为250-300nm，通过观察透明度和颜色，不同层数的二维材料薄膜可以在显微镜下被清楚的识别。然而，较厚的SiO₂层作为栅介质导致Si/SiO₂衬底上的二维材料背栅晶体管虽迁移率高但栅控非常差。为解决背栅晶体管栅控差的问题，普遍先在Si/SiO₂衬底上识别二维材料薄膜，再将其转移至其他需要的衬底，但大量的有机物污染会造成二维材料性能明显退化，背栅晶体管的迁移率难以提升。另一种方案是采用Si/high-k等具有高栅控的衬底，直接在高栅控衬底上制备背栅晶体管，亚阈值摆幅可接近玻尔兹曼极限(~70mV/dec)，但这些衬底的透明栅介质层太薄，不足以反射加强可见光，无法准确分辨二维材料的层数，难以应用于需要直接禁带，或对禁带宽度有特殊需求的光电器件或气体传感器等。 为降低背栅晶体管栅介质EOT的同时保留衬底二维材料层数和厚度的识别率，本论文提出了Si/SiO₂/氧化铟锡(Indium tin oxide， ITO)/high-k/FET结构，采用透明的ITO代替不透明的金属作为栅电极，透明层总光程差由SiO₂，ITO及high-k介质的光程差叠加，精确计算折射率和厚度使该衬底的总光程差与250nm-300nm SiO₂接近。使用Si/SiO₂/IT0/high-k衬底避免了二维材料在不同衬底间的转移带来的有机物污染，保持与Si/SiO₂衬底类似的二维材料质量和层数识别率，并提供了EOT足够低的栅介质使背栅晶体管能够具有接近玻尔兹曼极限的亚阈值摆幅。 本论文在Si/SiO₂/ITO/high-k衬底上制备了多组过渡金属硫化物(TMDs)场效应晶体管。各类TMDs二维材料薄膜在Si/SiO₂/ITO/high-k衬底上具有极高的质量、厚度辨识度，展现了优越的迁移率、接近玻尔兹曼极限的亚阈值摆幅(61mV/dec)、高开关比(~10⁷)和低工作电压(小于3V)，证明了Si/SiO₂/ITO/high-k衬底可极大地改善二维材料背栅器件的栅控、功耗和工作电压范围，并同时保留机械剥离法材料晶格完整、电学性能出众的优势。 随后，本论文在Si/SiO₂/ITO/high-k衬底上制备了两种用于可见光探测的单沟道光电晶体管：单层MoS₂光电晶体管和四层ReS₂光电晶体管。两组光电晶体管的光电响应率均高于已有同类文献最高值的五倍左右，其中单层MoS₂光电晶体管在关断区的低工作电压(-0.5V至1.5V)、高光电响应灵敏度(最高4000A/W)和高光暗电流开关比(最高650)为低功耗、直流、弱光源探测提供了良好的解决方案。 沿袭Si/SiO₂/ITO/high-k采用透明的ITO替代不透明电极，在硅衬底上叠加需要的透明层以适应机械剥离二维材料的识别的思路，本论文提出了以Si/SiO₂/ITO/HfZrO/ITO/high-k衬底为基础的MoS₂背栅负电容晶体管。MoS₂负电容晶体管相比于其对应的背栅晶体管有明显的栅控增强和沟道电流提升，最低亚阈值摆幅为42mV/deC，低于玻尔兹曼极限，证明了该方案的可行性，以及该衬底上获得高性能二维材料器件的可能性。 可拓展的结构除了本论文中提出的负电容晶体管，也可通过设计透明叠层方案尝试其他种类的二维材料背栅器件，例如Si/SiO₂/ITO/high-k上的气体传感器、Si/SiO₂/ITO/HfZrO上的铁电晶体管、Si/SiO₂/ITO/high-k/浮栅层/high-k上的存储器等。本论文为机械剥离二维材料器件结构提供了新思路，绕开了二维材料表面超薄顶栅介质制备困难和重复率差的问题，为研究各类二维材料的半导体性质拓展了一种可重复性高、适应性强的解决方案。 关键词：二维材料，过渡金属硫化物，背栅晶体管，光电晶体管，负电容晶体管。 中图分类号：TN303，TN305

 FETs with 2D semiconductor as channel were so far the most reproducible structures for studying the properties of 2D materials. Since the first back-gate graphene transistor was reported in 2004, back-gate FETs fabricated based on mechanical exfoliated 2D material samples have been extensively applied in studies for band structure, valleytronics and spintronics, electronic and optical properties and so forth. In most works, exfoliated 2D material samples were taped onto silicon substrate covered with 250-300nm thick SiO₂ film to build back-gate devices, because it was easy to locate and roughly identify the quality and layer number of the ultra-thin 2D flakes under the optical microscope. However, such FETs usually had poor gate control due to the thick SiO₂gate dielectrics. One extensively used solution to improving the gate control included transferring the exfoliated sample from Si/SiO₂ surface to other desired substrates. Nevertheless, the transfer process usually involved with spreading organic materials, leading to a degraded device behavior. Replacing SiO₂ by thin high-k film in the exfoliation substrates like Si/high-k substrate might be a perfect solution to 2D semiconductor FETs with greatly enhanced gate control (70mV/dec), if EOT (Equivalent Oxide Thickness) of high-k dielectric was low enough. While it was hard to identify the exact layer number of 2D flakes on such kind of substrates, so that it could seldom applied in optoelectronic devices or sensors, where direct band gap was essential to achieve high responsivity. In this work, Si/SiO₂/indium tin oxide (ITO)/high-k/FET structure was introduced, dedicated to solving the identification problem and reducing EOT of the gate dielectric at the same time. The thickness of SiO₂/ITO/high-k stack had been engineered to ensure that the optical identification of exfoliated 2D flake was very close to that on Si/SiO₂. With ultra-thin high-k film as gate dielectric and ITO as back gate, 2D FETs on Si/SiO₂/ITO/high-k substrate were expected to eliminate the contamination induced by transfer process, exhibit low subthreshold swing, and preserve the identification of 2D flakes. Experimentally, several TMDs back gate FETs based on Si/SiO₂/ITO/high-k substrate had been fabricated and characterized in this work. High mobility, low subthreshold swing (61mV/dec) and high on/off ratio (~10⁷) were observed, which indicated that Si/SiO₂/ITO/high-k substrate could preserve the non-defect property of mechanical exfoliation method, optimize the power consumption and improve the gate controllability of the transistors. After that, two types of direct-bandgap back-gate photodetectors were fabricated based on single-layer MoS₂ and four-layer ReS₂. Both photodetectors showed impressively high photo-responsivity, which were about five times better than that in previously reported works. In depletion area, the single-layer MoS₂ photodetector exhibited low working bias (from-0.5V to 1.5V),excellent photo sensitivity (4000A/W) and high on/off ratio (650), which suggested a promising solution to low-power and direct-current weak light detection. Following the idea of optimizing stacked transparent films for 2D flakes observation, MoS₂ negative capacitance FETs (NCFETs) on Si/SiO₂/ITO/HfZrO/ITO/high-k substrate were introduced in this work. The subthreshold swing (SS) had been improved in MoS₂ NCFETs, with minimum value of 42mV/dec, as well as on-state current. The performance of the devices well proved the feasibility of this 2D NCFET design, and the possibility of obtaining high quality 2D flakes on Si/SiO₂/ITO/HfZrO/ITO/high-k substrate. By designing the stacked transparent films on substrate, other types of 2D back gate devices could be achieved, such as gas sensor on Si/SiO₂/ITO/high-k, ferroelectric transistor on Si/SiO₂/ITO/HfZrO, flash memory on Si/SiO₂/ITO/high-k/floating gate/high-k, and so on. Results in this work provided a brand new idea for structure of exfoliated 2D back gate devices, bypassed the procedure of ultra-thin top gate dielectric growth on the surface of 2D flakes, which was still lack of reproducible up to now. The designed experiment in this work immensely enriched the use of 2D back gate devices in studies of the properties of 2D semiconductors. Keywords: Two-dimensional Materials,Transition Metal Dichalcogenides, Back Gate Transistor,Photodetector,Negative Capacitance Field-Effect Transistor. Chinese Library Classification Code: TN303,TN305