随着集成电路工艺尺寸按比例不断缩小，CMOS集成电路的集成度和工作速度也显著提高。然而当传统CMOS器件工艺尺寸下降到20nm以下，短沟道效应如阈值电压滚降、漏致势垒降低的剧烈增大，这限制了传统CMOS器件尺寸进一步下降。多栅MOSFET器件通过多个栅极对沟道的控制，减少短沟道效应，提高了器件的性能。FinFET器件是多栅MOSFET器件结构中的一种，其沟道受栅极两面或三面包围，增强了栅极对沟道的控制力度，极大的抑制了短沟道效应；采用零掺杂或低掺杂沟道，使得FinFET器件受工艺参数波动影响不明显；且制造工艺与CMOS器件制造工艺兼容。因此，FinFET器件成为集成电路工业界新一代的器件，使得工艺尺寸继续按摩尔定律持续下降。 独立栅FinFET器件是从公共栅FinFET器件变化来的，其前后两个栅极是独立控制沟道的。本文围绕独立栅FinFET器件进行探索研究，主要包括：独立栅FinFET器件特性、双阈值独立栅FinFET器件参数优化、基于双阈值独立栅FinFET器件的不同逻辑风格的数字电路低功耗设计。本学位论文内容主要包括： 1.研究独立栅FinFET器件参数对器件性能的影响，通过优化模型参数构建双阈值独立栅FinFET器件。本文一方面从物理特性上分析栅功函数、体硅厚度、栅氧化层厚度等器件工艺参数对阈值电压、亚阈值摆幅、导通电流、截止电流等器件性能的影响，另一方面通过HSPICE仿真验证器件工艺参数与器件性能的关系，为参数优化提供理论依据。对器件参数进行优化得到双阈值独立栅FinFET器件，通过对双阈值独立栅模式(independent-gate mode，IG)FinFET器件的性能进行分析，发现并联的两个同栅模式(short-gate mode，SG)FinFET器件可以用一个低阈值独立栅IG FinFET器件去代替，串联的两个同栅SG FinFET器件可以用一个高阈值独立栅IG FinFET器件去代替。 2.研究电路的拓扑结构对逻辑门电路性能的影响，提出双阈值独立栅IG FinFET静态互补逻辑电路。对于静态互补逻辑电路来说，采用双阈值独立栅IG FinFET实现相同的逻辑函数可以通过有多种不同的拓扑结构实现，同时电路性能会有很大的差异。本文比较和分析双阈值独立栅IG FinFET构成的互补逻辑基本门电路和复合逻辑门的多种不同的拓扑结构的电路性能，提出双阈值独立栅IG FinFET在静态互补逻辑电路的合并优化原则，并应用到一位全加器电路。仿真结果表明，新提出的电路结构功耗延时积减少了22.7％。本文还对几种触发器的电路进行结构优化，比较了优化前后的电路性能。 3.提出双阈值独立栅IG FinFET双轨电流模逻辑电路和单轨电流模逻辑电路。电流模逻辑电路具有恒定的电路功耗，与工作频率无关，和较小的输出摆幅等的优点，因此适用于高速应用场合。本文简要介绍电流模逻辑电路的电路结构、工作原理和电路性能，并对电流模逻辑电路的最小工作电压及主要特性参数进行了详尽的阐述。研究了电流模逻辑电路设计参数对电流模逻辑电路的性能影响。根据双阈值独立栅IG FinFET的特点，对双轨电流模逻辑电路和单轨电流模逻辑电路的下拉晶体管网络进行拓扑结构优化。仿真结果表明采用双阈值独立栅IG FinFET实现的双轨电流模逻辑和单轨电流模逻辑复合门电路和组合电路与同栅SG FinFET实现的相应的逻辑功能的电路相比，不仅晶体管数目得到了减少，而且在相同的电路功耗情况下电路时延也减少了10％-20％。 本学位论文构建了双阈值独立栅IG FinFET器件，开展了基于双阈值独立栅IG FinFET多种逻辑风格的电路低功耗设计理论与方法研究，是一项既具有理论学术价值，又有应用前景的研究课题。 关键词：独立栅FinFET，双阈值，器件参数，低功耗，电流模逻辑电路

 The integration density and operating speed of integrated circuits are enhanced significantly with continuous technology scaling. The short channel effects of the CMOS device, such as threshold voltage roll-off and drain-induced barrier lowering, increases sharply as its feature size is reduced below 20nm, and thus it is impossible for CMOS device to shrink the device dimension. Multi-gate MOSFET technologies mitigate the short channel effects and improve the device performance by providing a stronger control over channel with multiple coupled gates. FinFET is the most attractive choice among the multi-gate transistor architectures, because of lower short channel effect, lower leakage current, the similarity of the fabrication steps to the existing standard CMOS technology and weakened sensitivity to parameter variations for no doping or low doping channel. A variation of the standard common gate FinFET device is the independent gate FinFET device, in which two independently connected gates control an unique channel. In this dissertation, some problems of the independent gate FinFET circuit are explored, mainly includes: independent gate FinFET device characteristics, device parameter optimization of dual-threshold independent gate FinFET, the low power design of different logic styles digital circuit using dual-threshold independent gate IG FinFET. The main contents of this dissertation are listed as follows: 1.Influence of device parameters on device performance of independent gate FinFET is researched, dual-threshold independent gate FinFET device is obtained by device parameter optimization. On the one hand, we analyze the influence of process parameters such as gate work function, bulk silicon thickness and gate oxide thickness on threshold voltage, subthreshold swing, on-current, and leakage current of FinFET device from physical properties. On the other hand, we also verify the relationship of process parameters and device performance using HSPICE simulation, which can provide threoy basis for parameters optimization. The optimum values for these process parameters are derived for dual-threshold independent gate FinFET devices. By analysis the device performance of dual-threshold independent gate mode (IG) FinFET deevices, We found that two parallel short gate mode (SG) FinFETs can merge to one low threshold independent gate IG FinFET and two serial short gate SG FinFETs can merge to one high threshold independent gate IG FinFET. 2.Impaction of circuit topology on electrical performance of logic gates is researched and the dual-threshold independent gate IG FinFET static complementary logic circuits are proposed. For static complementary logic , Any logic gate can be implemented using several circuit topology base on independent gate IG FinFET,and electrical performance of different circuit topology is different. We firstly analysis and compare the electrical performance of basic logic gate and complex logic gate, then we propose a mergeing and optimizaiton method of dual-threshold independent gate IG FinFET. Static complementary one bit full adder circuit structure can be optimize using the proposed method. The simulation results show that the proposed circuit structure of static complementary one bit full adder obtained about 22.7% power-delay product savings compared with one bit full adder base on short gate SG FinFET. We also optimize several circuit structure of Flip-Flops and compare the electrical performance. 3.The dual-rail Current-mode logic circuits and single-rail current-mode logics based on dualthreshold independent gate IG FinFET are proposed. Current-Mode logic circuit is one of the most widely used logic styles in high-speed application because of low noise and constant static power consumption. Firstly, basic Current-mode logic circuit structure, operation principle and circuit performance are introduced. Then, the minimum supply voltage and performance parameters of Current-mode logic are analyzed. The influence of Current-mode logic design parameters on Current-mode logic performance parameters are also discussed in detail. The dual-rail Currentmode logic and single-rail Current-mode logic basic gate and combinational circuit of dualthreshold independent gate IG FinFET is optimized,its transistor count decreases by 30-50% and its dealy saves about 10-20% compared with the correspoding independent gate SG FinFET circuit. The dual-threshold independent gate IG FinFET device is constructed and the research of dual-threshold independent gate IG FinFET low power design theory and method based on several logic style circuit in this dissertation. Therefore, this subject has important academic significances and application values. Key Words: Independent Gate FinFET, Dual Threshold, Devices Parameters, Low Power, Current Mode Logic