随着CMOS图像传感器在智能手机和汽车等应用领域上的发展，获取2D色彩和光强信息的传感时代已经达到一定高度，而获取3D信息的技术和手段正处于起步阶段。研究3D成像的相关技术和原理，与国际同行同步竞争在3D图像传感器领域的关键技术研究和突破，于个人、于市场、于国家都是具有极其重要的意义。因此，本论文着眼于研究实现3D成像的CMOS图像传感器芯片。 本论文实现3D成像的方法是使用单光子雪崩二极管(SPAD)作为感光器件，搭配时间数字转换器(TDC)实现空间深度信息获取。本文设计的SPAD结构采用的是p+／深n-well结构的pn结，使用p-well作为保护环，采用八角形拓扑结构，其感光区域的横向长度是20μm。本文针对淬火复位电路(QRC)在对SPAD实现淬火和复位功能时存在的休眠时间和不稳定区域的理解，提出了新的休眠时间可调的淬火复位电路，其能够做到不稳定区域最小化的特点。该QRC在0.35μm高压CMOS工艺下实现，休眠时间可以在24ns到2.1μs灵活可调，且不稳定区域均小于10ns，占用面积为20×39μm²，耗用功耗均小于0.2mW。 TDC是使用SPAD实现3D成像必不可少的电路单元。本文根据已有的一些TDC架构存在的一些不足之处，提出了新型游标环形TDC。该新型游标环形TDC，使用本文所提出的脉宽限定型延迟单元作为环形延迟链的基本单元，该脉宽限定型延迟单元在外控制电压的控制范围内实现延迟时间范围是159ps到209ps。通过设定大小两个控制电压可实现双延迟环的一对延迟单元的延时时间差为11.25ps，即作为所设计的TDC的时间分辨率。此外，本文对游标环形TDC需要的可再生比较器提出了改进方案。同时，本文设计了新的结构紧凑的温度计码转换二进制码的转码电路，包括转译电路和编码电路。本文所设计的新型游标环形TDC在0.18μm CMOS工艺下实现，具有13bit的量化范围，所测得INL为1.22LSB，DNL小于0.2％LSB，所消耗功耗0.16mW，使用电源电压1.8V，占用面积仅为0.03㎜²。 本文根据所提出的休眠时间可调的QRC和所提出的游标环形TDC，优化其结构后，提出了适用于SPAD像素内的QRC和像素内的TDC，配合所提出的八角形SPAD感光单元，构成3D CMOS图像传感器最关键的像素单元。所提出的像素内QRC结构简单，其休眠时间可通过外部控制信号设置，而且不存在不稳定区域。所提出的像素内TDC采用单环振荡计数模式，最小时间分辨率为240ps，有效位数为14bit，有效测量范围为3.9μs。同时，像素内TDC可以越过环形振荡过程，实现对SPAD的雪崩事件计数，可以使用在其他应用需求上。最终在0.18μm的CMOS工艺下获得SPAD型的像素尺寸为56×66μm²，填充因子为8.96％。最终所设计的基于SPAD-TDC型像素的3D CMOS图像传感器芯片的像素阵列为32×32，芯片(包括IO)占用面积为2.6㎜×2.44㎜，芯片所能测试空间深度信息最大间距理论值是585m，可达到最小深度分辨率为72.2㎜。 关键词：单光子雪崩二极管，淬火复位电路，时间数字转换器，三维成像，CMOS图像传感器

 With the development of CMOS image sensors in applications of smart phones and automobiles, the era of 2D to capture color and light intensity information has reached a certain height now. While the technologies and methodes to obtain information of 3D environment are in the initial stage. Studying the relevant technologies and principles of 3D imaging sensors is vitally important. And to research and break through the key technologies in the field of 3D image sensors in synchronous competition with international counterparts is also vitally important.Therefore, this paper mainly studies and research the image sensor chip that realizes 3D imaging. In this paper, the method to achieve 3D imaging is to use single photon avalanche diodes (SPADs) as the photosensitive devices and to acquire spatial depth information with time to digital converters (TDCs). The SPADs are designed as octagonal topological structure in this paper. The pn junction is applied by p+/deep n-well structure for absorbing inping photons. P-well is used as the guard ring and around the pn junction. The transverse length of the photosensitive area is 20μm. In this paper, a novel quenching and reset circuit (QRC) with adjustable the hold-off time is proposed, which can minimized the unstable region improve in literatures. The QRC is realized in the 0.35μm high voltage CMOS technology. The hold-off time can be flexibly adjusted from 24ns to 2.1μs, and the unstable area is minimized less than 10ns. And the proposed QRC occupies the area of 20×39μm², with the power consumption always less than 0.2mW. TDC is an essential circuit unit for 3D imaging sersors using method of SPAD type. According to some shortcomings of existing TDC architectures, a new architecture of vernier ring TDC is proposed. The new vernier ring TDC uses the self-confined pulse width delay cell which is proposed in this paper as the basic unit of the dual-ring delay chains. The delay range of the self-confined pulse width delay cell is 159ps to 209ps within the control of the external control voltage. By setting the two control voltages, the delay time difference of a pair of delay cells of double delay rings can be 11.25ps, which is used as the time resolution of the proposed vernier ring TDC. In addition, an arbiter for the vernier ring TDC is proposed in this paper. And a new compact thermal-code-switching binary code transcoding circuit is proposed, including the translation circuit and the coding circuit. The new vernier circular TDC is realized under the 0.18μm CMOS technology, and has a quantitative range of 13bit. The maximum values of INL and DNL measured are 1.22LSB and less then 0.2%LSB, respectively. While the power consumption is as less as 0.16mW with the power supply is 1.8V and occupied area is 0.03 ㎜². Based on the proposed QRC with adjustable hold-off time and the proposed vernier ring TDC, the structure of QRC and TDC are optimized in the pixel with the proposed octagonal SPAD. which consist of the most critical pixel unit of 3D CMOS image sensor. The structure of in-pixel QRC is simple and compact, whose hold-off time can be set by external control signal with no unstable region. The in-pixel TDC adopts the singleloop oscillation counting mode, with a minimum time resolution of 240ps, an effective range of 14bit and an effective measurement time range of 3.9μs. What's more, the inpixel TDC can bypass the circular oscillation process and realize count of the avalanche events of the SPADs, which can be used in other application requirements. Finally, under the 0.18μm CMOS process, the pixel size of SPAD is obtained as 56μm×66μm, and the filling factor is 8.96%. The 3D CMOS image sensor chip based on the SPAD pixels is designed with an array of 32×32. The chip (including IO) occupies an area of 2.6㎜×2.44㎜, and a theoretical maximum measurement of depth of 585m. reaching a minimum depth resolution of 72.2㎜. Key Words: single photon avalanche diode (SPAD), quenching and reset circuit (QRC), time to digital converter (TDC), 3D imaging, CMOS imaging sensors.